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Code Portability and Related Issues for EPIC
The new Itanium chip from Intel is being called an EPIC architecture
(Explicitly Parallel Instruction Computing) in contrast to RISC
(Reduced Instruction Set Computing) and CISC (Complex Instruction Set
Computing) architectures. This lecture considers implications of the
new architecture for code portability and performance.
Speaker: |
Our speaker will be
Robert Gezelter,
a Senior Member of IEEE and a member of the
IEEE Computer Society’s
Distinguished Visitors Program.
Mr. Gezelter holds BA and MS degrees in Computer Science
from New York University. He is a contributor to the
Computer Security Handbook (2002)
and the Handbook of Information Security (2005). He has spoken and written extensively on
operating systems, networks, performance, security, tools, and similar areas.
Mr. Gezelter is in private practice, and maintains his offices in Flushing, New York.
He can be contacted via his firm’s www site at
http://www.rlgsc.com.
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Sponsors: |
IEEE Green Mountain Section and Computer Society
Dartmouth College, Hanover, New Hampshire
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Venue: |
Dartmouth College, Moore, Room B03
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Date: |
Monday, September 26, 2005
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Time: |
4:00 PM to 5:30 PM
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Press Release: |
http://www.rlgsc.com/ieee/Vermont/2005-09/PressRelease.pdf
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Reservations: |
Christopher Masone
christopher.p.masone-at-dartmouth.edu, Subject: IEEE DVP RSVP
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Session Notes: |
http://www.rlgsc.com/ieee/Vermont/2005-09/codeportability.html
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